Dr. Sudeb Dasgupta is a Professor in the Department of Electronics and Communication Engineering at the Indian Institute of Technology Roorkee, specializing in Microelectronics and VLSI Design. He earned his Ph.D. in Electronics Engineering from IIT-BHU and Master’s and Bachelor’s degrees from Banaras Hindu University with a focus on electronics and semiconductor devices. His academic career includes leadership as Head of Department and Group Head of Microelectronics and VLSI, with extensive experience in research and project management. Dr. Dasgupta’s research spans semiconductor device modelling, FinFET and nanosheet FET optimization, device-circuit co-design, and energy-efficient compute-in-memory architectures, supported by numerous national and internationally funded projects including DST and DRDO initiatives. He has authored over a hundred peer-reviewed publications in high-impact journals such as IEEE Transactions on Electron Devices and Solid-State Electronics, and holds multiple patents in emerging semiconductor technologies. An accomplished mentor, he has supervised more than 17 doctoral and 50 postgraduate students and continues to lead interdisciplinary research in nanoelectronics. Dr. Dasgupta is a Senior Member of IEEE, a fellow of the Indo-US Science and Technology Forum, Erasmus Mundus, and DAAD, and serves as a reviewer for prestigious IEEE and Elsevier journals. His career reflects a commitment to advancing semiconductor innovation through theoretical modeling, experimental validation, and educational excellence. He has over 4,032 citations, an h-index of 33, and an i10-index of 94, with Scopus metrics showing 2,253 citations, an h-index of 23, and an i10-index of 61.
Profile: Google Scholar
Featured Publications
Sudeb Dasgupta*, The role of dielectric wall in Forksheet FET: Exploring electrical-thermal intercoupling. IEEE Trans. Dielectr. Electr. Insul., 2025.
Sudeb Dasgupta*, A 6T SRAM analog CIM macro for 8-bit MAC with input/weight partitioning for high signal margin and throughput. IEEE APCCAS Conf., 2025.
Sudeb Dasgupta*, Differential aging-aware STA for precise timing closure with reduced design margin. IEEE Trans. Device Mater. Reliab., 2025.
Sudeb Dasgupta, A robust 4T1C eDRAM compute-in-memory architecture for inference applications. IEEE NEWCAS Conf., 2025.