Professor Xiaoteng Zhao of Xidian University is a leading expert in high-speed data interfaces and chiplet interconnects, recognized for advancing integrated circuit design in next-generation wireline communication systems. He holds advanced degrees in microelectronics and integrated circuit engineering with specialization in high-speed mixed-signal architectures, and his professional experience includes serving as principal investigator for major national research initiatives, directing innovations in reconfigurable chiplet interconnects, multi-level high-speed receivers, and energy-efficient communication circuits. He has led teams in developing record-breaking transceiver designs and contributed extensively to the field through influential publications in premier IEEE venues such as ISSCC, JSSC, CICC, and RFIC. His research spans CDR systems, PLL architectures, frequency dividers, multi-mode EOMs, analog front-end techniques, and wireline link optimization, supported by more than twenty patents and impactful collaborative projects. His achievements have earned multiple honors, including best paper recognition and national-level commendation for semiconductor research advancements. In addition to his technical contributions, he has served on editorial boards, participated in IEEE standardization efforts, taken on TPC roles, and maintained active membership in professional engineering societies, reinforcing his leadership and service to the microelectronics community. Quote 257, h-index 9, i10-index 8.
Profile: Google Scholar
Featured Publications
X. Zhao, Y. Dong, Y. Zhang, H. Chang, Y. Qi, Z. Yang, C. Han, H. Liang, Y. Yu, A Full-Rate 8.2-to-15.1-Gb/s Reference-Less CDR using Low-Cost SAR-Based Frequency Acquisition Technique Achieving 265 ns Acquisition Time. Microelectronics Journal, 106944, 2025.
Z. Yang, X. Zhao, H. Sun, X. Su, Z. Dong, Y. Dong, Y. Yu, H. Liang, S. Liu, A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator. Microelectronics Journal, 106870, 2025.
J. Liu, X. Su, Z. Yang, Z. Dong, C. Han, X. Zhao, S. Liu, A 7-bit 8 GHz Phase Interpolator With Eight-Phase Output Using a Linear Weighting Scheme Using Only 50% Interpolation Units. Microelectronics Journal, 106874, 2025.
M. Zhang, R. Li, X. Zhao, X. Su, Z. Dong, Z. Yang, H. Su, H. Liang, Y. Yu, S. Liu, Load-Driven Inductive Peaking Design for Broad Band Continuous-Time Linear Equalizer. Microelectronics Journal, 106873, 2025.
Z. Dong, X. Zhao, Z. Yang, X. Su, H. Han, F. Bu, D. Sun, S. Liu, Z. Zhu, A 0.0006-mm² 0.13-pJ/bit 9–21-Gb/s Sub-Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS. IEEE J. Solid-State Circuits, 2025.